Bare Metal:          A platform with no operating system, often just a single processor with a fully populated memory space. Often the platform is used with a basic semihost library and referred to as a user-mode simulation.

Binary interception: The monitoring by a simulator of the execution of application code by a processor model so that the simulator can change its behavior without having to modify the application.

Core:                   Autonomous execution unit, usually defined by having its own program counter (PC).

Cycle Accurate Model: A model that represents the implementation details of a processor including its pipelines, and cycle by cycle state changes. (as opposed to Instruction Accurate)

Debug target:    Execution unit that is recognized by a debugger. Usually equivalent to a Core, but might not be.

DMI:                  Direct Memory Interface. (In TLM2.0) circumvention of the transaction mechanism, giving a processor model direct access to a memory model. When enabled this can speed up a simulation by orders of magnitude, but loses the ability to observe or analyze bus transactions.

Extendable Platform Kit               Virtual Platform available from Imperas that comes with full documentation, source, and example Operating Systems running.

Instance:          Copy of the part of a model that holds its state.  Some simulators can load a model once, then simultaneously simulate several instances without interference between them.

Instruction Accurate Model: A model that represents the functionality of a processors instruction execution without regard to artifacts like pipelines. Only instruction boundaries are visible. (as opposed to Cycle Accurate).

Instruction Set Simulator:  (ISS) A program that when run executes a model of a CPU allowing its instructions to be executed. Normally allows some connection to a debugger, and normally includes modeling of program/data memory and no peripherals.

MIPS:              Million Instructions Per Second. A measure of processor speed (not to be confused with MIPS Technologies, Inc, a  processor IP vendor).

Model:             Software simulation model of a processor or processor family.

Multicore:         A processor containing more than one core.

OVPsim:          Simulator that implements a subset  of the OVP APIs, available from the OVPworld website.

Platform:           Software model of a complete circuit comprising processors, memory, buses and peripherals. The simulation is accurate enough for software development but not for accurately predicting system performance..

Processor:        Indivisible device provided by a silicon vendor or licensor. Can be supplied as RTL, layout or finished silicon.

Quantum:          (In multiprocessor simulation) A time period in which each processor in turn simulates a certain number of instructions. Simulated time is advanced only at the end of a quantum, so this is limit of timing accuracy of the simulation. The quantum is usually fixed for the duration of a simulation, but can be changed (at the start of a new quantum).

Semihosting:     Interception by the simulator of calls in the application to I/O functions and the passing of the calls to the host operating system.

Software Virtual Prototype: as Platform.

Sparse memory: Simulated memory is created by the OVP simulator as it is used; unused regions are not allocated. Therefore the simulator can create a model of a memory larger than that of the host computer.

System Virtual Prototype: as Platform.

TLB:                Translation Look-aside Buffer. Part of a processor’s VM controller.

Variant:            A configuration setting of a model to represent a specific vendor processor, for example to configure the generic MIPS model to be MIPS 24KEc.

Virtual Platform: as Platform.

Virtual Prototype: as Platform.

VM:                 Virtual Memory or Virtual Memory controller. Hardware that allows a processor to simultaneously execute several programs without interfering with each other.

Multiprocessor Simulation:  Processors in multiprocessor platforms do not execute simultaneously; for efficiency each processor advances a certain number of instructions in turn. Increasing the number of instructions run on one processor in one turn (quantum) will reduce the time spent by the simulator switching context, so will improve simulation speed. However, it will also increase the chance that interactions between processors will be inaccurate with respect to the timing, especially if they communicate through shared memory. This mechanism is used in C, and C++, and SystemC TLM.0 platforms.

Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes.

FamilyVirtual Platform / Virtual Prototype
ARM Based Platforms    BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle AlteraCycloneV_HPS ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx AlteraCycloneV_HPS ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel iMX6S Zynq_PS
MIPS Based Platforms    BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle HeteroArmNucleusMIPSLinux MipsMalta MipsMalta
Vendor Platforms    BareMetalNios_IISingle AlteraCycloneIII_3c120 AlteraCycloneV_HPS AlteraCycloneIII_3c120 AlteraCycloneV_HPS BareMetalArcSingle BareMetalArm7Single BareMetalArmCortexADual BareMetalArmCortexASingle BareMetalArmCortexASingleAngelTrap BareMetalArmCortexMSingle ArmIntegratorCP ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 ArmIntegratorCP ARMv8-A-FMv1 ArmVersatileExpress ArmVersatileExpress-CA15 ArmVersatileExpress-CA9 AtmelAT91SAM7 AtmelAT91SAM7 FreescaleKinetis60 FreescaleKinetis64 FreescaleVybridVFxx Or1kUclinux ArmCortexMFreeRTOS ArmCortexMuCOS-II HeteroArmNucleusMIPSLinux ArmCortexMFreeRTOS ArmCortexMuCOS-II ArmuKernel ArmuKernelDual Quad_ArmVersatileExpress-CA15 RiscvRV32FreeRTOS BareMetalM14KSingle BareMetalMips32Dual BareMetalMips32Single BareMetalMips64Single BareMetalMipsDual BareMetalMipsSingle MipsMalta MipsMalta iMX6S BareMetalOr1kSingle BareMetalM16cSingle BareMetalPowerPc32Single BareMetalV850Single ghs-multi RenesasUPD70F3441 ghs-multi RenesasUPD70F3441 virtio FaultInjection Zynq_PL_DualMicroblaze Zynq_PL_NoC Zynq_PL_NoC_node Zynq_PL_NostrumNoC Zynq_PL_NostrumNoC_node Zynq_PL_RO Zynq_PL_SingleMicroblaze Zynq_PL_TTELNoC Zynq_PL_TTELNoC_node XilinxML505 XilinxML505 zc702 zc706 Zynq Zynq_PL_Default Zynq_PS